1. Field of the Invention
The present invention generally relates to an over-heat protecting circuit, and in particular, to an over-heat protecting circuit and its system circuit board for protecting an over-heat CPU.
2. Description of the Prior Art
With science being developed and updated day by day, computers have being integrated into parts of our lives. Almost all the professional works rely on such tool so as to be efficient. On the other hand, the clock speeds of CPUs have being shifted from million is times per second to billion times per second. Not only the components and the circuits are more complicated, but also the heavy source codes are increasing from millions of lines to billions of lines.
A South Bridge chipset is embedded in the present motherboard, which controls most of the low-speed devices in the system, such as ISA (Industry Standard Architecture), IDE (Integrated Device Electronics), USB (Universal Serial Bus), PCI (Peripheral Component Interconnect), etc. Additionally the South Bridge chipset connects and controls the power supplier as well.
Refer to FIG. 1, which illustrates a circuit block diagram of a system circuit board in prior arts. The system circuit board 100 has a CPU 102, a South Bridge chipset 104, and a power supplier 106; wherein the South Bridge chipset 104 electrically connects the CPU 102 and the power supplier 106, and there is an over-heat protecting circuit (not shown in the figure) in the South Bridge chipset 104.
In the prior art, the CPU 102 outputs an over-heat signal to the South Bridge chipset 104 while detecting the temperature of the CPU 102 over a predetermined temperature. After the over-heat signal being processed by the over-heat protecting circuit, a turn-off signal from the CPU 102 is sent to the power supplier 106 so as to stop providing power to the system circuit board 100 and simultaneously prevent the condition of damaging the CPU 102.
FIG. 2 illustrates that the over-heat protecting circuit is embedded in the South Bridge chipset. In FIG. 2, the system circuit board 200 has a CPU 202, a super IO controller 204, a South Bridge chipset 206, a BIOS 208, and a power supplier 210.
In the prior art, the CPU 202 outputs an over-heat signal to the super IO controller 204 while detecting the temperature of the CPU 202 over a predetermined temperature. The over-heat signal from the super IO controller 204 is thus sent to the South Bridge chipset 206. After the over-heat signal being processed by the over-heat protecting circuit, a turn-off signal from the South Bridge chipset 206 is delivered to the power supplier 210 so as to stop providing power to the system circuit board 200 and simultaneously prevent the condition of damaging the CPU 202.
As mentioned above, the two embodiments in prior arts have the same point, that is, both the over-heat protecting circuit are embedded in the South Bridge chipset; the only difference between them is that the CPU 202 in FIG. 2 outputs the over-heat signal to the super IO controller 204, and then to the South Bridge chipset 206.
Please refer to FIG. 3, which illustrates another circuit block diagram of the system circuit board in prior arts. In the embodiment of FIG. 3, an over-heat protecting circuit 304 is independently installed in the system circuit board 300. Since the over-heat signal is not transmitted to the South Bridge chipset, additional circuits may be a must to turn off the power supplier 306. Traditionally such way can only turn off the power supplier 306 for milliseconds, and the system circuit board 300 may be restarted constantly, or the system is turned off after 4 seconds, hence this is not conform to the requirement of shutting down the system within 0.5 second.
The system circuit board 300 has a CPU 302, an over-heat protecting circuit 304, a power supplier 306, and a super IO controller 308; wherein the over-heat protecting circuit 304 electrically connects the CPU 302, the power supplier 306, and the super IO controller 308.
With references to FIG. 3 and FIG. 4, FIG. 4 is a practical circuit diagram of FIG. 3.
In the prior art, the over-heat protecting circuit 304 has a plurality of transistor Q2 to transistor Q5, a plurality of resistor R4 to resistor R7, a capacitor C2, an AND gate 402, and a flip-flop 404. Wherein the resistor R7 receives a memory voltage (V_SM1), the resistor R6 receives an operating voltage (VCC3), the resistors R4 and R5, the flip-flop 404, and the AND gate 402 receive a plurality of backup powers, and a base electrode of the transistor Q4 receives an over-heat signal from the CPU. While turning on the system, the over-heat signal is at logic high; otherwise, it is at logic low.
According to different power suppliers 306, the memory voltage (V_SM1) is randomly raised up slower than the operating voltage (VCC3) so as to possibly pull down the over-heat signal (THERMTRIP_L) to logic low, which is enabled by the transistor Q2, but it causes that the system is irregularly turned off due to the malfunction of the over-heat signal (THERMTRIP_L).
TABLE 1over-heatover-heat signalsignal/powerpower-controlof CPUbutton signalsuper IO signalsignalHHLL (powersupplier ON)LLLH (powersupplier OFF)HHHH (powersupplier OFF)LLHH (powersupplier OFF)
With reference to Table 1, which shows the plurality of states of logic potential of the over-heat signal of the CPU (CPU_THERMTRIP_L), the over-heat signal (THERMTRIP_L)/the power button signal (PWRBTN_L), the super IO signal (SIO_ONCTL_L), and the power-control signal (PSON_L). Wherein H represents the state of high logic potential and L represents the state of low logic potential.
After the system is normally turned on and operated for a while, continuously the CPU 302 detects a temperature thereof over a predetermined temperature, and the over-heat signal of the CPU (CPU_THERMTRIP_L) may be pull down to logic low. The over-heat signal of the CPU (CPU_THERMTRIP_L) is thus divided into two signals, the over-heat signal (THERMTRIP_L) and the power button signal (PWRBTN_L), and transmitted along two paths after the logic levels of the transistors Q2 and Q5 are transformed.
Referring to the first path, the AND gate 402 receives the over-heat signal (THERMTRIP_L) and the super IO signal (SIO_ONCTL_L) inverted by the inverter 404. Subsequently the AND gate 402 generates an invert signal to turn off the power supplier 306, meanwhile the power-control signal (SPON_L) is at logic high.
On the other hand, while the super IO controller 308 detects the condition of power fail, the super IO signal (SIO_ONCTL_L) handled by the super IO controller may be raised to logic high after the BIOS processing around 0.5 to 20 seconds so as to distinctly turn off the power supplier 306.
While the power-control signal (PSON_L) is converted to logic high, as shown in Table 1, the over-heat signal (THERMTRIP_L) is immediately converted to logic high due to the conditions of power fail and capacitor residue voltage (the transistor Q2 is disabled). Alternatively, the super IO signal (SIO _NCTL_L) is not converted to logic high by the super IO controller 308 yet, the power-control signal (PSON_L) is then converted to the state of low logic potential in order to restart the power supplier 306. Hence the purpose of turning off may not be achieved.
The second path is for a forced turn-off operation according to the power button signal (PWRBTN_L). As shown in the prior arts, the forced turn-off operation of the system may need 4 seconds, which does not meet the requirement of shutting down the system within 0.5 second.